Parametric yield optimization of CMOS analogue circuits by quadratic statistical circuit performance models

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  1. Department of Statistics
  2. Parametric yield optimization of CMOS analogue circuits by quadratic statistical circuit performance models

Parametric yield optimization of CMOS analogue circuits by quadratic statistical circuit performance models

TitleParametric yield optimization of CMOS analogue circuits by quadratic statistical circuit performance models
Publication TypeJournal Article
AuthorsYu, TK, Kang, SM, Sacks, J, Welch, WJ